1. Field of the Invention
The present invention relates to integrated circuit manufacturing techniques and particularly to plastic encapsulation techniques for of electrically and thermally enhanced integrated-circuit package designs.
2. Prior Art
Conventional integrated circuit devices are commonly manufactured by attaching an integrated-circuit die to a lead frame. The lead frame includes a centrally located die-attach paddle, upon which the integrated-circuit die is mounted. The lead frame also includes a plurality of conductive leads, the inner ends of which converge at the die-attach paddle. Bonding finger portions at the inner ends of the leads are used to make electrical connections between the integrated-circuit die and the conductive leads of the lead frame. The entire assembly described above is encapsulated in a molded plastic material to form a molded-plastic body.
As semiconductor technologies improve, individual semiconductor circuit devices become smaller, allowing for greater die packing densities and increased operating speeds. However, these advancements present new problems as well. For example, as operating speeds increase, the inductance of the leads of the lead frame causes signal cross-talk and ground bounce. Additionally, as die densities increase, additional heat is produced by the die which can result in decreased operating performance or even failure of the integrated-circuit die.
As the operating speeds of the circuits on an integrated-circuit die increase, the inductance problems become more significant. Inductance can cause the VSS voltage on a ground bus to vary as various devices within the integrated circuit are switched on and off. Inductance in the leads of the integrated circuit and the lead frame can cause the VSS voltage to vary on the ground bus. This variation is referred to as ground bounce and degrades the high speed performance of the integrated circuit.
One technique for reducing inductance is to designate a number of leads or conductors which are connected in parallel. This increases the number of I/O package pins being required.
Another technique for reducing inductance is to use a multilayer printed-circuit substrate. This type of package is extremely expensive due to high manufacturing costs and low production yields for the printed circuit substrate.
A number of techniques have been used to alleviate the problems caused by heat buildup in a densely packed integrated-circuit die. One technique uses a thermally-conductive, electrically-insulated substrate to which the integrated-circuit die is attached. The bottom surface of the die is attached to the top surface of the thermally conductive substrate so that the thermally conductive substrate can transfer heat away from the integrated-circuit die. The thermally-conductive, electrically-insulated substrate is formed, for example, of a material such as alumina nitride. For good thermal operation, the thermally conductive substrates are relatively thick, significantly thicker than the die-attach paddle of a conventional lead frame.
However, because of this increased thickness and bulk of the substrate, the thicker thermally conductive substrates can impede or restrict the flow of the plastic molding compound to certain areas of the mold during encapsulation of the integrated circuit. The plastic molding material flows more freely over the top of the integrated circuit than under the integrated circuit. As a result of differences in flow rates, the air which is forced through the molds by the molding compound may be trapped on the bottom side of a package, which leaves blowholes or voids in the body of the molded package. Consequently, use of the thicker thermally conductive substrates has created moldability problems, such as formation of voids.
Consequently, the need exist for an integrated-circuit package configuration which has improved thermal performance, reduced inductance, and superior moldability characteristics.